| Nominal Frequency |
1.000MHz to 155.520MHz
Some frequencies within this range may not be available. |
| Frequency Tolerance/Stability |
(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating Temperature Range,
Supply Voltage Change, Output Load Change, First Year Aging at 25°C, Shock, and Vibration)
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
±20ppm Maximum
|
| Operating Temperature Range |
0°C to +70°C
-40°C to +85°C
|
| Supply Voltage (VDD) |
5.0VDC ±10% |
| Input Current |
50mA Maximum (No Load) |
| Output Voltage Logic High (VOH) |
IOH = -16mA
2.4VDC Minimum with TTL Load, VDD-0.4VDC Minimum with HCMOS Load
|
| Output Voltage Logic Low (VOL) |
IOL = +16mA
0.4VDC Maximum with TTL Load, 0.5VDC Maximum with HCMOS Load |
| Duty Cycle |
50 ±10(%) (Measured at 1.4VDC with TTL Load or at 50% of wavform with HCMOS Load over Nominal Frequency
range of 1MHz to 70MHz; Measured at 50% of waveform over Nominal Frequency range of 70.000001MHz to
155.52MHz)
50 ±5(%) (Measured at 50% of waveform with TTL Load or with HCMOS Load)
|
| Rise Time/Fall Time |
Measured at 0.8VDC to 2.0VDC with TTL Load, 20% to 80% of waveform with HCMOS Load
6nSec Maximum over Nominal Frequency of 1MHz to 70MHz
4nSec Maximum over Nominal Frequency of 70.000001MHz to 155.52MHz
|
| Load Drive Capability |
10TTL Load or 50pF HCMOS Load Maximum over Nominal Frequency of 1MHz to 70MHz
5TTL Load or 15pF HCMOS Load Maximum over Nominal Frequency of 70.000001MHz to 155.52MHz |
| Output Logic Type |
CMOS |
| Pin 1 Connection |
Tri-State (Disabled Output:High Impedance)
|
| Tri-State Input Voltage (Vih and Vil) |
+2.2VDC Minimum to enable output, +0.8VDC Maximum to disable output (High Impedance), No Connect to enable
output. |
| Absolute Clock Jitter |
±250pSec Maximum, ±100pSec Typical |
| One Sigma Clock Period Jitter |
±50pSec Maximum, ±30pSec Typical |
| Start Up Time |
10mSec Maximum |
| Aging (at 25°C) |
±5ppm/year Maximum |
| Storage Temperature Range |
-55°C to +125°C |