EN13C7 Series Test Circuit

Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass capacitor close (less than 2mm) to the package ground and supply voltage pin is required.

Note 2: A low input capacitance (<12pF), 10X Attentuation Factor, High Impedance (>10Mohms), and High bandwidth (>500MHz) passive probe is recommended.

Note 3: Test circuit PCB traces need to be designed for a characteristic line impedance of 50 ohms.

Note 4: A 10 ohm to 33 ohm series resistor is required to limit overshoot. Rs value is circuit layout dependant.