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EQRG12 Series Oscillator
Quartz Crystal Clock Oscillators XO (SPXO) HCSL 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

Revision  C  06/26/2014

Electrical Specifications

Nominal Frequency 10.000MHz to 200.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C, Shock, and Vibration
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
±20ppm Maximum
Operating Temperature Range 0°C to +70°C
-20°C to +70°C
-40°C to +85°C
Aging at 25°C ±3ppm Maximum First Year
Supply Voltage 2.5VDC ±5%
Input Current Without Load
30mA Maximum
Output Voltage Logic High (VOH) 580mVDC Minimum, 740mVDC Typical, 850mVDC Maximum
Output Voltage Logic Low (VOL) -150mVDC Minimum, 0mVDC Typical, 150mVDC Maximum
Duty Cycle Measured at 50% of waveform
50 ±10(%)
50 ±5(%)
Rise Time/Fall Time Measured at 0.175VDC to 0.525VDC of waveform
500pSec Maximum
Output Swing (dVOpp) 600mV Minimum, 740mV Typical, 850mV Maximum
Load Drive Capability Between Output and Ground
50 Ohms
Output Logic Type HCSL
Phase Noise Click to Open Phase Noise Table
Output Control Function Standby (on Pad 1)
Standby (on Pad 2)
Output Control Input Voltage Logic High (Vih) 70% of VDD Minimum or No Connect to Enable Output and Complementary Output
Output Control Input Voltage Logic Low (Vil) 30% of VDD Maximum to Disable Output and Complementary Output (High Impedance)
Standby Output Enable Time 10mSec Maximum
Standby Output Disable Time 200nSec Maximum
Standby Current Without Load
10µA Maximum
RMS Phase Jitter Click to Open RMS Phase Jitter Table
Period Jitter (Deterministic) 0.2pSec Typical
Period Jitter (Random) 1.0pSec Typical
Period Jitter (One Sigma) 1.5pSec Typical
Period Jitter (tp-p) 40pSec Maximum
Storage Temperature Range -55°C to +125°C
Start Up Time 10mSec Maximum