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EV32C6 Series Oscillator
Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVCMOS/TTL (CMOS) 3.3Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

Revision  N  04/14/2014

Electrical Specifications

Nominal Frequency 1.544MHz to 77.760MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, Shock, and Vibration)
±50ppm Maximum
Operating Temperature Range 0°C to +70°C
-40°C to +85°C
Supply Voltage (VDD) 3.3VDC ±10%
Input Current 15mA Maximum
Output Voltage Logic High (VOH) IOH = -4mA
90% of VDD Minimum
Output Voltage Logic Low (VOL) IOL = +4mA
10% of VDD Maximum
Duty Cycle Measured at 50% of waveform
50 ±5(%) Typical, 50 ±10(%) Maximum
Rise Time/Fall Time Measured at 20% to 80% of Waveform
5nSec Maximum
Load Drive Capability 10TTL Load or 30pF LVCMOS Load Maximum over Nominal Frequency of 1.544MHz to 12.288MHz
15pF LVCMOS Load Maximum over Nominal Frequency of 12.288001MHz to 77.76MHz
Output Logic Type CMOS
Absolute Pull Range Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, Shock, Vibration, and Aging over the Control Voltage (Vc).
±50ppm Minimum
±80ppm Minimum (Only available over Nominal Frequency range of 1.544MHz to 51.84MHz)
±100ppm Minimum (Only available over Nominal Frequency range of 1.544MHz to 36MHz)
Control Voltage Test Condition for Absolute Pull Range
0.3VDC to 3.0VDC
Control Voltage Range 0.0VDC to VDD
Linearity 10% Typical, 20% Maximum
Transfer Function Positive Tranfer Characteristic
Modulation Bandwidth Measured at -3dB, Vc = 1.65VDC
10kHz Minimum
Input Impedance 50kOhms Minimum
Input Leakage Current 10µA Maximum
Phase Noise All Values are Typical
-70dBc/Hz at offset of 10Hz, -100dBc/Hz at offset of 100Hz, -130dBc/Hz at offset of 1kHz, -147dBc/Hz at offset of 10kHz, -152dBc/Hz at offset of 100kHz, and -155dBc/Hz at offset of 1MHz
Tri-State Input Voltage (Vih and Vil) 90% of VDD Minimum or No Connect to Enable Output, 10% of VDD Maximum to Disable Output (High Impedance)
RMS Phase Jitter Fj = 12kHz to 20MHz; Random
1pSec Maximum
Aging (at 25°C) ±2ppm/First Year Typical, ±10ppm/10 Years Maximum
Storage Temperature Range -55°C to +125°C
Start Up Time 10mSec Maximum